1. Field
Embodiments described herein relate generally to a memory system and a control method for the same configured to perform encoding processing on data and store the data as coded data and to perform decoding processing on coded data when reading the coded data, and more particularly, to a memory system and a control method for the same configured to use LLR tables to perform decoding processing through probability-based repeated calculations.
2. Description of the Related Art
In memory systems that include a host and a storage apparatus having a semiconductor memory section, data encoding processing and decoding processing are performed with error correcting codes.
Error correcting codes can be roughly divided into algebra-based hard decision decoding codes such as BCH codes or RS codes, and soft decision decoding codes using probability-based repeated calculations. Low density parity check codes (hereinafter referred to as “LDPC codes”) belonging to soft decision decoding codes are becoming a focus of attention. For LDPC codes, excellent performance approaching a Shannon limit, which is a theoretical limit of code performance, has been reported.
Here, in storage apparatuses having a NAND-type semiconductor memory section, storage of data of a plurality of bits in one memory cell or what is called multivalue memory greatly contributes to increasing the storage density. In the multivalue memory, data is read when a threshold voltage corresponding to the amount of charge injected into a charge storage layer of each memory cell is applied to a word line.